1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a nonvolatile semiconductor memory device having a protect feature against data rewriting. More particularly, the present invention relates to a structure for setting a protection mode on data programming and erasure.
2. Description of the Background Art
A semiconductor memory device is advantageous over a memory device that uses a magnetic disc as a storage medium by virtue of its small size, lightweight, and high speed access, and has a wider application. A nonvolatile semiconductor memory device that stores information in a nonvolatile manner is known as one such semiconductor memory device. This nonvolatile semiconductor memory device has the stored information retained even when the power is turned off. It is used as a program memory or data memory in equipments such as a portable information terminal that employs a battery as the power source. A well known example of a nonvolatile semiconductor memory device is a flash EEPROM (electrically erasable and programmable read only memory: referred to as flash memory hereinafter) having a memory cell formed of one transistor, and that allows increase in integration density and collective erasure of data in a certain address range.
It is premised that information is stored in a nonvolatile manner in the nonvolatile semiconductor memory device such as a flash memory. It is therefore necessary to prevent the nonvolatile data from being rewritten by erroneous programming and erasure. Particularly in the case where the nonvolatile semiconductor memory device is used as a program memory, the stored data must be reliably retained, and any erroneous programming and erasure had to be obviated. For the purpose of preventing erroneous programming and erasure, a "write protect" feature is provided in a nonvolatile semiconductor memory device such as a flash memory. This write protect feature allows a user to apply a lock for any programming and erasing operation on a certain data region (memory block) that should not be written or erased. The write protect feature prevents erroneous programming and erasure on a memory block basis. Here, the term "write" is used as including the erasure step of erasing a memory cell data and the programming step of actually writing data into an erased memory cell.
FIG. 13 schematically shows a structure of the portion related to the writing/erasing operation of a conventional nonvolatile semiconductor memory device. Referring to FIG. 13, a nonvolatile semiconductor memory device includes a memory array 100 having a plurality of nonvolatile memory cells for storing information in a nonvolatile manner, and a protect control data storage region 102 for storing information indicating inhibition/permission of writing and erasure of a nonvolatile memory cell in memory array 100.
Memory array 100 is divided into a plurality of memory blocks 100a-100n. Erasure is carried out block by block.
Protect control data storage region 102 includes a plurality of lock bit storage units 102a-102n provided corresponding to memory blocks 100a-100n, respectively. Lock bit storage units 102a-102n store lock bits LBa-LBn, respectively, indicating inhibition/permission of writing and erasing with respect to corresponding memory blocks 100a-100n. The values of lock bits LBa-LBn indicate whether programming/erasure of memory blocks 100a-100n is allowed or not. Therefore, the writing/erasing operation can be inhibited on a block-by-block basis.
The conventional nonvolatile semiconductor memory device further includes a program/erasure control circuit 103 receiving a chip enable signal /CE, a reset power down mode signal /RP, a write protect signal /WP and a block address signal for controlling the programming/erasing operation of a memory block specified by the block address signal according to lock bits LBa-LBn stored in protect control data storage region 102, and a program/erase circuit 105 for carrying out erasure/programming on a memory block (or page) specified by the address signal under control of program/erasure control circuit 103.
Program/erasure control circuit 103 determines whether a write/erase operation mode is specified or not according to the states of reset power down mode signal /RP and write protect signal /WP when chip enable signal /CE is active. If a write/erase operation is specified, a lock bit LB (LBa-LBn) is read out from the lock bit storage unit provided corresponding to the memory block that is specified by the block address signal, whereby inhibition/permission of write/erasure with respect to the addressed memory block is determined. When a write/erasure operation is permitted, program/erasure control circuit 103 generates a voltage required for programming/erasing and provides the generated voltage to program/erasure circuit 104.
Program/erasure circuit 104 includes an X decoder and a Y decoder that selects a block and a memory cell in memory array 100 according to an address signal.
In the conventional nonvolatile semiconductor memory device, the write protect feature that provides protection with respect to writing and erasing operations has these operations controlled according to reset power down mode signal /RP, write protect signal /WP, and the state of lock bit LB read out from the addressed memory block.
As shown in FIG. 14, memory array 100 is divided into a plurality of regions 100br, 100pr, and 100mr, each including at least one memory block. The nonvolatile semiconductor memory device stores program and data. Allocation of memory blocks to each storage region is determined according to the attribute (or type) of the stored data. In FIG. 14, memory array 100 is divided into a boot block region 100br for storing a boot code and the like that is required at the time of initialization when the power is turned on, a parameter block region 100pr for storing numeric parameters such as a telephone number and identification number that is uniquely used by a manufacturer and a personal user, and a main block region 100mr for storing data that is to be rewritten arbitrarily during actual usage. In the array division structure shown in FIG. 14, a write protect feature as shown in FIG. 15 is implemented according to external control signals /RP and /WP and the lock bit as described below.
(i) When reset power down mode signal /RP is set to a boosted level HH that is higher than the voltage level of a logical high level (H level) in a normal operation mode, writing or erasure can be carried out on all memory blocks 100a-100n in memory array 100 regardless of the state of write protect signal /WP and the value of lock bit LB. The value of lock bit LB can also be rewritten. The writing/erasure of the data in memory array 100 and the writing/erasure (rewriting) of lock bit LB are specified by a command.
(ii) When reset power down mode signal /RP and write protect signal /WP are both set at an H level, writing and erasing can be carried out on boot block region 100br, parameter block region 100pr and main block region 100mr regardless of the value of lock bit LB. Also, writing/erasure can be carried out on lock bit LB.
(iii) When reset power down mode signal /RP is at an H level and write protect signal /WP is at a logical low level (L level) of the ground voltage, writing/erasure is inhibited/permitted according to the value of a corresponding lock bit LB provided for respective memory blocks 100a-100n. When the value of lock bit LB indicates a lock state, writing and erasure on the corresponding memory block is inhibited. When the value of lock bit LB indicates an unlock state, writing and erasing can be carried on the corresponding memory block. Also, the value of lock bit LB can be rewritten.
(iv) When reset power down mode signal /RP is at an L level, the nonvolatile semiconductor memory device is set to a power down mode, so that internal operation is inhibited. In this power down mode, the nonvolatile semiconductor memory device attains a standby state, so that consumed current is reduced. Under this circumstance, no rewriting of the stored information should occur. Data rewriting (including writing and erasing) of all the memory cells in boot block region 100br, parameter block region 100pr and main block region 100mr in memory array 100 is inhibited regardless of the value of lock bit LB. Similarly, the value of lock bit LB also cannot be rewritten.
The usage of lock bit LB allows the writing and erasing operation to be inhibited/permitted (lock/unlock) by every memory block. The stored data can be prevented from being rewritten by erroneous erasure and programming. Thus, the required data can be reliably retained.
Inhibition/permission of writing and erasing on a memory block basis can be specified by lock bit LB. The validity/invalidity of lock bit LB, i.e., whether writing or erasing is to be carried out independent of the value of lock bit LB, can be set by externally applied control signals, namely reset power down signal /RP and write protect signal /WP. Under the above-described conventional lock control for providing the control of inhibition/permission of writing and erasing, the lock control status is determined in common to all the block regions of the boot block region, the parameter block region, and the main block region according to external control signals /RP and /WP. More specifically, there are three states of (i) permitting writing and erasing on all memory cells of memory array 100 regardless of the value of lock bit LB; (ii) determine inhibition/permission according to lock bit LB; and (iii) inhibiting writing and erasing regardless of the value of lock bit LB. In boot block region 100br of memory array 100, the boot program code for initializing the system (equipment: an entire equipment incorporating the nonvolatile semiconductor memory device) when the power is turned on and the control program code required for an interruption process and the like are stored. Reset power down mode signal /RP is set to an HH level when the information required for the nonvolatile semiconductor memory device (referred to as "data" hereinafter including both the code and data) is to be written. This setting is implemented by the manufacturer. In general, reset power down mode signal /RP will not be set to an HH level by a general user (HH level corresponds to a voltage of a further higher level than the normal H level).
Specific numeric parameters such as the identification number, time information and the like for the nonvolatile semiconductor memory device are stored in parameter block region 100pr. Additionally, information depending on the application such as the identification number of a personal user, the password number of an IC card, for example, the telephone number of a portable telephone, or the telephone number and address data for implementing the memorandum feature of a portable information terminal are stored in parameter block region 100pr. In main block region 100mr, audio information for realizing an answer telephone function, and image information of a digital camera and the like according to its application are stored, which can be constantly used and rewritten by the general user. The stored data includes data that must not be rewritten and data that may be rewritten.
However, in the conventional nonvolatile semiconductor memory device shown in FIG. 15, there is a possibility of erroneous writing and erasing where data that should not be rewritten is erroneously altered since inhibition/permission of writing and erasing is set in common to all the memory blocks in memory array 100 when used by the general user. For example, when signals /RP and /WP are both set at an H level, writing/erasing can be carried out on each region of memory array 100. Therefore, the data in all the memory blocks can be rewritten. In this case, there is a possibility of erroneous writing/erasing since the write protect feature is disabled. When signals /RP and /WP are set to an H level and an L level, respectively, the inhibition/permission of writing/erasing is controlled according to the value of lock bit LB. However, the value of lock bit LB can be modified. This means that there is a possibility of erroneous writing/erasing when an erroneous value of lock bit LB is set since control of inhibition/permission of writing/erasing is carried out according to the set value of lock bit LB.
In order to ensure that the numeric parameter once set in the parameter block region is not rewritten during the usage by a general user, it is preferable to control writing/erasing according to the value of lock bit LB as to the writing/erasing operation on a memory block in main block region 100mr while setting a lock state for parameter block region 100pr. However such lock control cannot be realized in the conventional nonvolatile semiconductor memory device shown in FIG. 15.
Furthermore, when a programming or erasing operation is carried out, inhibition of rewriting the value of lock bit LB cannot be specified. There is a possibility of setting lock bit LB for another memory block to an unlock state, which will result in erroneous writing/erasure.
Thus, it was difficult to prevent erroneous writing/erasing reliably when the lock status is set using a reset power down mode signal /RP and a write protect signal /WP.